EP1S20F672C7 vs EP1S20B672C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C7 sa pamamagitan ng Intel at EP1S20B672C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20F672C7 | EP1S20B672C6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Series | Stratix | EP1S20 |
| Family | Altera Stratix FPGA | Stratix |
| Logic Elements (LEs) | 18,460 | — |
| Embedded Memory Bits | 1,669,248 | — |
| User I/O Pins | 426 | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Packhaging | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) | 672-ball BGA (672-BBGA), 35 x 35 mm, 1.27 mm pitch |
| Logic Family | CMOS, SRAM-based | — |
| Core Supply Voltage | 1.5 V | — |
| Temperature na Operasyon | 0C to 85C (commercial) | 0 C to +85 C (Commercial) |
| Speed Grade | C7 | 6 |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | unknown | Compliant |
| Clock PLLs | Up to 10 | — |
| Logic Elements (LE) | — | 18,460 |
| Logic Array Blocks (LAB) | — | 1,846 |
| Embedded Memory | — | 1,669,248 bits |
| Maximum User I/O | — | 426 |
| Process Technology | — | 130 nm CMOS |
| Core Voltage | — | 1.5 V |
| Configuration Method | — | Passive Serial / Fast Passive Parallel / JTAG |
| Katayuan ng Lifecycle | — | Not Recommended for New Designs (NRND) |