EP1S20F672I7 vs EP1S20F672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672I7 sa pamamagitan ng Intel at EP1S20F672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera
EP1S20F672I7 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP1S20F672I7 | EP1S20F672C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Family | Stratix (first generation) | Altera Stratix FPGA |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Maximum RAM Bits | 1,669,248 | — |
| DSP Blocks | [DATA_NEEDED: exact DSP block count] | [DATA_NEEDED: DSP block count] |
| Maximum User I/Os | 426 | — |
| Supply Voltage (VCCINT core) | 1.5 V | — |
| Logic Family | CMOS | CMOS, SRAM-based |
| Packhaging | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Temperature na Operasyon | -40C to +85C (industrial grade, I7 suffix) | 0C to 85C (commercial) |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Number of Pins / Balls | 672 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Clock Management PLLs | [DATA_NEEDED: PLL count] | — |
| Tindminan RoHS | unknown | unknown |
| Lead-Free / Finish | SnPb (e0 per Partstack datasheet extract) | — |
| Level ng MSL | unknown | [DATA_NEEDED: MSL level] |
| Status | Last Time Buy (per distributor notices) | — |
| Series | — | Stratix |
| Embedded Memory Bits | — | 1,669,248 |
| User I/O Pins | — | 426 |
| Core Supply Voltage | — | 1.5 V |
| Speed Grade | — | C7 |
| Clock PLLs | — | Up to 10 |