EP1S25F672C7N vs EP1S20B672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25F672C7N sa pamamagitan ng Altera at EP1S20B672C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S25F672C7N | EP1S20B672C7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Stratix | — |
| Logic Elements (LEs) | 25,660 | 18,460 |
| Logic Array Blocks (LABs) | 2,566 | — |
| Embedded Memory Bits | 1,944,576 | 1,669,248 bits |
| Maximum User I/O | 473 | 426 |
| Number of I/O Pins | 672 (BGA balls) | — |
| Packhaging | 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch | — |
| Process Technology | 0.13 µm CMOS | 0.13 µm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| I/O Supply Voltage (VCCIO) | [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] | — |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | 0 °C to 85 °C (Commercial Extended) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Configuration Method | JTAG / Passive Serial / Active Serial | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | 3 (per JEDEC J-STD-020) |
| Tindminan RoHS | [DATA_NEEDED: confirm from product page] | [DATA_NEEDED: RoHS compliance] |
| Series | — | Stratix |
| Family | — | Stratix (original) |
| LABs / CLBs | — | 1,846 |
| Number of Pins / Balls | — | 672 |
| Package Type | — | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core, VCCINT) | — | 1.5 V |
| Speed Grade | — | -7 |
| Logic Family | — | CMOS |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |