EP1S25F780I6N vs EP1S30F780I6N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25F780I6N sa pamamagitan ng Intel at EP1S30F780I6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1S25F780I6N EP1S30F780I6N
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family Stratix Stratix
Logic Elements 25,660 32,470
Logic Array Blocks (LABs) 2,566 —
Total RAM Bits 1,944,576 3,317,184 bits
User I/O Pins 597 —
Packhaging 780-BBGA (FineLine BGA, 29 x 29 mm, 1.0 mm pitch) —
Process Technology 130 nm CMOS 130 nm
Core Voltage 1.5 V —
Speed Grade 6 (I6 - industrial) -6
Temperature na Operasyon 0C to 85C (industrial) -40C to +100C (Industrial, I6)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Level ng MSL 3 (per Partstack listing) 3 (per typical FBGA moisture sensitivity)
Lead Free Yes (per Ampheo listing) —
Tindminan RoHS [DATA_NEEDED: rohs status] —
DSP Blocks Yes (dedicated 9/18/36-bit multipliers) Yes (TriMatrix + DSP blocks per Stratix family)
Embedded PLL Yes —
LVDS Support Yes (up to 840 Mbps per Altera datasheet family) —
Configuration Mode JTAG / Passive Serial / Fast Passive Parallel (per Stratix family) —
User I/O Count — 597
Package Type — 780-BBGA, FCBGA (FineLine BGA)
Supply Voltage (Core) — [DATA_NEEDED: core voltage]
I/O Standards Supported — LVTTL, LVCMOS, LVDS, SSTL, HSTL
Lead-Free / RoHS — Lead-free terminal finish (N suffix), RoHS-compliant
JEDEC Code (e1) — e1 (Pb-free / matte tin)

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