EP1S30F780I6N vs EP1S40F780I6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S30F780I6N sa pamamagitan ng Intel at EP1S40F780I6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S30F780I6N - Stratix FPGA, 32.5K LE, 780-BGA | Intel / Altera
EP1S30F780I6N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1S30F780I6N | EP1S40F780I6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | — |
| Logic Elements | 32,470 | 41,250 |
| Total RAM Bits | 3,317,184 bits | 3,423,744 |
| User I/O Count | 597 | — |
| Package Type | 780-BBGA, FCBGA (FineLine BGA) | — |
| Temperature na Operasyon | -40C to +100C (Industrial, I6) | -40C to +100C (industrial) |
| Process Technology | 130 nm | — |
| Supply Voltage (Core) | [DATA_NEEDED: core voltage] | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL | — |
| Lead-Free / RoHS | Lead-free terminal finish (N suffix), RoHS-compliant | — |
| Speed Grade | -6 | — |
| DSP Blocks | Yes (TriMatrix + DSP blocks per Stratix family) | 12 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 (per typical FBGA moisture sensitivity) | 3 |
| JEDEC Code (e1) | e1 (Pb-free / matte tin) | — |
| Series | — | Stratix |
| Logic Array Blocks (LABs) | — | 4,125 |
| User I/O Pins | — | 615 |
| Core Voltage (VCCINT) | — | 1.425 V to 1.575 V |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| PLLs | — | [DATA_NEEDED: PLL count per Stratix handbook] |
| Embedded Multipliers | — | Yes (per DSP block) |
| Configuration Method | — | SRAM-based, volatile |
| Packhaging | — | 780-FBGA (29 x 29 mm, 1.0 mm pitch) |
| Lead Free | — | Yes |
| Process Node | — | 150 nm CMOS |
| Tindminan RoHS | — | Compliant |