EP1S40F1020C5 vs EP1S40F1020C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S40F1020C5 sa pamamagitan ng Intel at EP1S40F1020C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S40F1020C5 | EP1S40F1020C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix | Stratix |
| Series | Stratix I | — |
| Logic Elements | 41,250 | 41,250 |
| Logic Array Blocks (LABs) | 4,125 | — |
| Maximum User I/Os | 773 | — |
| Embedded Memory | 3.4 Mbits (TriMatrix) | — |
| DSP Blocks | Yes (dedicated hardware multipliers) | Yes (dedicated 9x9 / 18x18 / 36x36 multipliers) |
| Process Technology | 130 nm | 130 nm CMOS |
| Core Voltage | 1.425 V to 1.575 V | — |
| Speed Grade | C5 | — |
| Packhaging | 1020-ball FC-FBGA (33 mm x 33 mm) | 1020-ball FC-FBGA (33 x 33 mm, 1 mm pitch) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0 C to 85 C (Commercial) |
| Maximum Internal Clock | up to 500 MHz | 420.17 MHz |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS, PCI | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance for EP1S40F1020C7] |
| Typical Gates | — | 412,500 |
| CLBs | — | 4,697 |
| Embedded Memory Bits | — | 3,423,744 |
| Maximum User I/O | — | 773 |
| Core Supply Voltage | — | 1.5 V |
| TriMatrix Memory | — | M512 / M4K / M-RAM blocks |