EP1S40F780C7N vs EP1S40F780I6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S40F780C7N sa pamamagitan ng Intel at EP1S40F780I6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S40F780C7N | EP1S40F780I6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | — |
| Logic Elements | 41,250 | 41,250 |
| Embedded Memory (bits) | 3,423,744 | — |
| Maximum User I/O | 615 | — |
| Operating Supply Voltage (Core) | 1.5 V | — |
| Process Technology | 130 nm CMOS | — |
| Speed Grade | 7 | — |
| Temperature na Operasyon | 0 C to +85 C (Commercial) | -40C to +100C (industrial) |
| Packhaging | 780-BBGA, FC-FBGA, 29 x 29 mm, 1.0 mm pitch | 780-FBGA (29 x 29 mm, 1.0 mm pitch) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| DSP Blocks | 14 | 12 |
| Maximum Performance | 420 MHz | — |
| PLLs | Up to 12 | [DATA_NEEDED: PLL count per Stratix handbook] |
| LVDS Data Rate (max) | 840 Mbps per channel | — |
| Configuration Modes | PS, PPA, PPS, JTAG | — |
| I/O Standards | LVDS, LVPECL, PCI-X, HSTL, SSTL, LVTTL, LVCMOS | — |
| TriMatrix Memory | Yes (three block sizes) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Series | — | Stratix |
| Logic Array Blocks (LABs) | — | 4,125 |
| Total RAM Bits | — | 3,423,744 |
| User I/O Pins | — | 615 |
| Core Voltage (VCCINT) | — | 1.425 V to 1.575 V |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Embedded Multipliers | — | Yes (per DSP block) |
| Configuration Method | — | SRAM-based, volatile |
| Level ng MSL | — | 3 |
| Lead Free | — | Yes |
| Process Node | — | 150 nm CMOS |