EP1S80B956C5N vs EP1S80B956C6AB Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S80B956C5N sa pamamagitan ng Intel at EP1S80B956C6AB sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S80B956C5N | EP1S80B956C6AB |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Stratix | Stratix |
| Logic Elements | 79,040 | — |
| Maximum Internal Clock Frequency | 500 MHz | — |
| Process Technology | 130 nm CMOS | 130 nm |
| Core Supply Voltage | 1.5 V | — |
| Packhaging | 956-ball FCBGA | 956-ball FCBGA |
| Temperature na Operasyon | 0 °C to +85 °C (commercial, 'C' grade) | [DATA_NEEDED: operating temperature range] |
| Speed Grade | 5 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Memory Architecture | TriMatrix on-chip memory | — |
| DSP Blocks | Yes (dedicated hardware multipliers) | Embedded DSP blocks (per Stratix family) |
| PLLs | Yes (multiple) | Multiple PLLs for clock management |
| I/O Standard Support | LVDS, LVTTL, LVCMOS, SSTL, HSTL (per Stratix family) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements (LEs) | — | 79,040 |
| Logic Cells | — | 79,040 |
| Core Voltage | — | 1.5 V |
| Maximum Operating Frequency | — | 450.05 MHz |
| User I/O Pins | — | 683 |
| Memory Blocks | — | TriMatrix embedded RAM |
| Configuration Method | — | SRAM-based, configured via JTAG or passive/active serial |
| Manufacturer | — | Intel (formerly Altera) |