EP1SGX25DF1020C6ESL vs EP1SGX25DF1020C6ES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX25DF1020C6ESL sa pamamagitan ng Altera at EP1SGX25DF1020C6ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP1SGX25DF1020C6ES EP1SGX25DF1020C6ES - Stratix GX FPGA, 25K LE, FBGA-1020 | Altera

EP1SGX25DF1020C6ES - Stratix GX FPGA, 25K LE, FBGA-1020 | Altera

EP1SGX25DF1020C6ES ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP1SGX25DF1020C6ESL EP1SGX25DF1020C6ES
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family Stratix GX Stratix GX
Logic Elements 25,660 25660 cells
Total RAM Bits 1,944,576 bits [DATA_NEEDED: total RAM bits]
User I/O Pins 607 —
LABs/CLBs 2,566 —
Packhaging 1020-BBGA (FineLine BGA) FBGA-1020, 33 mm × 33 mm, 1.00 mm pitch
Core Voltage 1.5 V —
Temperature ng Junction na Operasyon 0 C to 85 C —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm RoHS]
Configuration Method Passive Serial / Fast Passive Parallel / JTAG —
Process Node 0.13 um CMOS —
Transceivers Embedded multi-gigabit transceivers (per Stratix GX family) —
DSP Blocks Yes (embedded DSP blocks) Yes
Speed Grade C6 —
I/O Standards Supported LVTTL, LVCMOS, SSTL, HSTL, LVDS (per family) —
Configurable Logic Blocks (CLBs) — 2566
Maximum User I/Os — 607
Number of LABs/CLBs — 2566
Temperature na Operasyon — 0 C to 85 C
Supply Voltage (Core) — 1.5 V
Process Technology — 130 nm CMOS
Logic Family — CMOS
Lead-Free — Yes
Configuration Interface — JTAG / Passive Serial / Passive Parallel
Embedded Transceivers — Yes (multi-gigabit)

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