EP1SGX40CF1020I5 vs EP1SGX40DF1020I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX40CF1020I5 sa pamamagitan ng Altera at EP1SGX40DF1020I7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP1SGX40DF1020I7 - 41,250 LEs Stratix GX FPGA, 1.5V FC-FBGA-1020 | Altera
EP1SGX40DF1020I7 ObsoletePagsanggunian na paghahambing
| Parametro | EP1SGX40CF1020I5 | EP1SGX40DF1020I7 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | Stratix GX | — |
| Family | Stratix (first generation) | Stratix GX |
| Logic Elements | 41,250 | 41,250 |
| Configurable Logic Blocks (CLBs) | 4,125 | 4,125 |
| Total RAM Bits | 3,423,744 | — |
| Number of Logic Cells / Gates | [DATA_NEEDED: gate count equivalent] | — |
| Process Technology | CMOS | 130 nm CMOS |
| Supply Voltage (Core) | 1.5 V | — |
| Number of Transceivers | 624 (per DigiKey listing family variant) | — |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Package Type | FBGA-1020 (FineLine BGA) | — |
| Package Dimensions | 33 mm x 33 mm | — |
| Ball Pitch | 1.0 mm | — |
| Temperature na Operasyon | -40C to +100C (industrial, I suffix) | -40 °C to +100 °C (I7 grade per family datasheet) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: confirmed RoHS per Intel/Altera] | [DATA_NEEDED: RoHS status] |
| Configuration Memory | SRAM-based (external config device required) | — |
| Speed Grade | 5 | — |
| Device Family Suffix Decoding | C = standard logic, F = enhanced, I = industrial temp | — |
| Nominal Core Supply Voltage | — | 1.5 V |
| Supply Voltage Range | — | 1.425 V to 1.575 V |
| Packhaging | — | 1020-ball FC-FBGA |
| Terminal Form | — | Ball |
| Package Shape | — | Square |
| Grading of Temperature | — | Military (I7 grade) |
| Technology | — | CMOS |
| Combinatorial CLB Delay | — | 9.48 ns (per family datasheet) |