EP1SGX40DF1020C6 vs EP1SGX40DF1020C5ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX40DF1020C6 sa pamamagitan ng Altera at EP1SGX40DF1020C5ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP1SGX40DF1020C6 - Stratix GX 41,250 Cells FPGA, 624 I/O | Altera
EP1SGX40DF1020C6 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP1SGX40DF1020C6 | EP1SGX40DF1020C5ES |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Series | Stratix GX | — |
| Family | Stratix GX FPGA | — |
| Manufacturer | Altera (Intel) | — |
| Logic Cells | 41,250 | 41,250 cells |
| Number of LABs/CLBs | 4,125 | — |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | — |
| Number of I/O | 624 | — |
| Voltage - Supply | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | 0 C to 85 C |
| Packhaging / Kaso | 1020-BBGA, FCBGA (FC-FBGA) | — |
| Supplier Device Package | 1020-FBGA (33 x 33 mm, 1 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Process Technology | 130 nm CMOS | 130 nm |
| Maximum Internal Performance | 5000 MHz (per datasheet rating) | — |
| Logic Family | CMOS, SRAM-based configuration | Stratix GX |
| Programmable Type | In-System Programmable (SRAM) | — |
| High-Speed Transceivers | Embedded (per Stratix GX family) | — |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | — |
| Packaging | Bulk / Tray | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Product Type | — | Field-Programmable Gate Array (FPGA) |
| Logic Technology | — | CMOS |
| Logic Array Blocks | — | 4,125 LABs |
| Configurable I/O Connections | — | 624 input and 624 output connections |
| Volte ng Pagbibigay | — | 1.5 V |
| Reported Maximum Frequency | — | 5,000 MHz |
| Reported Maximum CLB Combinatorial Delay | — | 7.49 ns |
| Alternative Listed Maximum Clock Frequency | — | 6 MHz |
| Terminal Count | — | 1,020 pins |
| Package Type | — | FC-FBGA-1020 |
| Package Dimensions | — | 33 mm x 33 mm |
| Ball Pitch | — | 1 mm |
| Mounting Configuration | — | Surface-mount ball grid array |
| Terminal Form | — | Ball |
| Package Code | — | BGA |
| Configuration Method | — | [DATA_NEEDED: configuration method] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |