EP1SGX40DF1020C6 vs EP1SGX40G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX40DF1020C6 sa pamamagitan ng Altera at EP1SGX40G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP1SGX40DF1020C6 - Stratix GX 41,250 Cells FPGA, 624 I/O | Altera
EP1SGX40DF1020C6 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP1SGX40DF1020C6 | EP1SGX40G |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | Stratix GX | — |
| Family | Stratix GX FPGA | Stratix GX |
| Manufacturer | Altera (Intel) | — |
| Logic Cells | 41,250 | — |
| Number of LABs/CLBs | 4,125 | — |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | 3,423,744 |
| Number of I/O | 624 | — |
| Voltage - Supply | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Packhaging / Kaso | 1020-BBGA, FCBGA (FC-FBGA) | — |
| Supplier Device Package | 1020-FBGA (33 x 33 mm, 1 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Process Technology | 130 nm CMOS | [DATA_NEEDED: process node] |
| Maximum Internal Performance | 5000 MHz (per datasheet rating) | — |
| Logic Family | CMOS, SRAM-based configuration | — |
| Programmable Type | In-System Programmable (SRAM) | — |
| High-Speed Transceivers | Embedded (per Stratix GX family) | — |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | — |
| Packaging | Bulk / Tray | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements | — | 41,250 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Maximum User I/O Pins | — | 624 |
| Packhaging | — | 1020-pin FineLine BGA |
| Number of Transceivers | — | 20 |
| Maximum Transceiver Data Rate | — | 3.1875 Gbps |
| Minimum Transceiver Data Rate | — | 500 Mbps |
| Transceiver Channels per Bank | — | 4 |
| Supported Serial Standards | — | PCI Express, XAUI, Serial RapidIO, SerialLite II |
| 8B/10B Encoder/Decoder | — | Hardware (dedicated per channel) |
| PLLs | — | [DATA_NEEDED: PLL count] |
| Speed Grades Available | — | C5, C6, C7, I5, I6, I7 |
| Operating Temperature Range (Commercial) | — | 0C to +85C |
| Operating Temperature Range (Industrial) | — | -40C to +100C |
| Configuration Method | — | EPC enhanced configuration devices, JTAG |
| Vertical Migration | — | Supported within 1020-pin FineLine BGA package (EP1SGX25/EP1SGX40) |