EP20K1000CF672I8 vs EP20K1000CF672C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K1000CF672I8 sa pamamagitan ng Intel at EP20K1000CF672C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K1000CF672I8 | EP20K1000CF672C8 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Manufacturer | Intel (formerly Altera) | — |
| Process Technology | 0.15 µm CMOS | 0.15 um all-layer copper CMOS |
| System Gates | 1,000,000 | 1,000,000 |
| Logic Elements / Cells | 38,400 | 38,400 |
| Packhaging | 672-pin FC-FBGA (FineLine BGA) | 672-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch |
| Ball Pitch | 1.00 mm | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| User I/O Count | 508 | — |
| Dedicated Inputs | 4 | — |
| Internal Frequency (max) | 301.21 MHz | — |
| Pin-to-Pin Logic Delay | 8 ns | — |
| Temperature na Operasyon | -40 °C to +85 °C (industrial, I suffix) | 0C to 85C (commercial) |
| Uri ng Memory | SRAM-based (volatile) | — |
| Embedded Memory | Embedded Array Blocks (EABs) for dual-port RAM / FIFO | — |
| PLL Count | 4 | — |
| I/O Standards | LVTTL, LVCMOS, PCI, SSTL, HSTL | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown (legacy part, verify on lot) |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Series | — | APEX 20KC |
| Embedded RAM | — | 327,680 bits |
| User I/Os | — | 488 (datasheet), 508 (per some distributor listings) |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Number of Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Number of PLLs | — | 4 |
| Maximum User I/O Pins | — | 488 |
| Core Voltage (VCCINT) | — | 1.8 V (typical) |
| I/O Voltage (VCCIO) | — | Multi-voltage (LVTTL/LVCMOS/LVDS/SSTL/GTL+ compatible) |
| Propagation Delay (typical) | — | 1.6 ns |
| Configuration Mode | — | FPP / Passive Serial / JTAG |