EP20K100CB356C8 vs EP20K100EBC356-3N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100CB356C8 sa pamamagitan ng Intel at EP20K100EBC356-3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K100CB356C8 EP20K100EBC356-3N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family APEX 20K APEX 20K
Logic Elements 4,160 —
Typical Gates 100,000 —
Maximum User I/O 252 —
Embedded Array Blocks (EABs) 12 —
Embedded Memory (EAB-based) 24 Kbits —
Phase-Locked Loops (PLLs) 4 —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0 °C to +85 °C
Packhaging 356-ball LBGA 356-LBGA (Ball Grid Array)
Process Technology 0.18 µm CMOS 0.22 µm CMOS
Configuration Modes PS / PPS / PPA / JTAG (IEEE 1532) —
Speed Grade C8 —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs_status]
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Level ng MSL [DATA_NEEDED: MSL level] —
Series — APEX-20KE
Logic Elements / Cells — 4160
System Gates — 100,000
Embedded Memory (bits) — 53,248
Embedded System Blocks (ESBs) — 26
Maximum User I/Os — 246
Bilang ng Pins — 356
Package Dimensions — 45 x 45 mm
Ball Pitch — 1.27 mm
Core Supply Voltage — 1.8 V
Propagation Delay — 1.6 ns (speed grade -3N)
Maximum Internal Frequency — 250 MHz
Programmable Interface — JTAG (IEEE 1149.1)
I/O Standards Supported — LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+

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