EP20K100CF144C7ES vs EP20K100CT144C7ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100CF144C7ES sa pamamagitan ng Intel at EP20K100CT144C7ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K100CT144C7ES - APEX-20K 100K Gate FPGA, 93 I/O, 144-LQFP | Altera
EP20K100CT144C7ES NrndPagsanggunian na paghahambing
| Parametro | EP20K100CF144C7ES | EP20K100CT144C7ES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | APEX-20K | — |
| Typical Gates | 100,000 | — |
| Logic Elements | 4,160 | 4,160 |
| Embedded Memory (RAM bits) | 53,248 | — |
| User I/O Pins | 93 | 93 |
| DLLs / Clock Management | 4 DLLs | — |
| Packhaging | 144-LQFP (20x20 mm) | 144-LQFP (20x20 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Speed Grade | C7 (commercial, mid-speed) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | 0C to +85C (Commercial) |
| Core Voltage | 1.8 V (typical APEX-20K VCCINT) | — |
| I/O Voltage Reference | MultiVolt I/O - 3.3 V / 5 V tolerant | — |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming File Format | Quartus II / MAX+PLUS II SOF / POF | — |
| Variant Suffix | ES (engineering sample / special order) | — |
| Level ng MSL | [DATA_NEEDED: MSL Level] | 3 |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (per Besenchips listing) |
| Series | — | APEX-20K |
| Core Voltage (VCCINT) | — | 2.375 V to 2.625 V |
| Typical Gate Count | — | 100,000 gates |
| Total RAM Bits | — | 53,248 bits |
| Process Technology | — | 0.18 µm CMOS |
| MultiVolt I/O Levels | — | 1.8 V, 2.5 V, 3.3 V, 5 V |
| Configuration Interface | — | IEEE 1149.1 JTAG |
| Lead-Free | — | Yes |