EP20K100CT144C9 vs EP20K100CT144C7ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100CT144C9 sa pamamagitan ng Altera at EP20K100CT144C7ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K100CT144C7ES - APEX-20K 100K Gate FPGA, 93 I/O, 144-LQFP | Altera
EP20K100CT144C7ES NrndPagsanggunian na paghahambing
| Parametro | EP20K100CT144C9 | EP20K100CT144C7ES |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX-20K | — |
| Device Logic Elements | 4,160 | — |
| Typical Gates | 100,000 | — |
| Embedded Memory (RAM bits) | 53,248 | — |
| Maximum User I/O | 93 | — |
| Packhaging | 144-LQFP | 144-LQFP (20x20 mm) |
| Speed Grade | -9 | — |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Core Voltage (VCCINT) | 2.5 V | 2.375 V to 2.625 V |
| I/O Voltage (VCCIO) | 3.3 V | — |
| Process Technology | 0.22 um CMOS | 0.18 µm CMOS |
| Number of PLLs | 4 | — |
| Configuration Method | SRAM / JTAG (IEEE 1149.1) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Compliant (per Besenchips listing) |
| Series | — | APEX-20K |
| Typical Gate Count | — | 100,000 gates |
| Logic Elements | — | 4,160 |
| Total RAM Bits | — | 53,248 bits |
| User I/O Pins | — | 93 |
| MultiVolt I/O Levels | — | 1.8 V, 2.5 V, 3.3 V, 5 V |
| Configuration Interface | — | IEEE 1149.1 JTAG |
| Level ng MSL | — | 3 |
| Lead-Free | — | Yes |