EP20K100FC324-2 vs EP20K100FC324-3 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100FC324-2 sa pamamagitan ng Intel at EP20K100FC324-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
EP20K100FC324-2 EP20K100FC324-2 - APEX 20K 100K Gates FPGA | Intel / Altera

EP20K100FC324-2 - APEX 20K 100K Gates FPGA | Intel / Altera

EP20K100FC324-2 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP20K100FC324-2 EP20K100FC324-3
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Device Family APEX 20K —
Equivalent Gates 100,000 —
Logic Cells 4,160 —
Maximum User I/Os 252 —
Packhaging 324-ball FBGA 324-pin FBGA (Fine-pitch BGA)
Bilang ng Pin 324 —
Technology Node 0.22 µm CMOS —
Core Supply Voltage 2.5 V 2.5 V
Propagation Delay (tPD) 1.6 ns —
Internal Performance 200 MHz —
Temperature na Operasyon 0°C to 85°C 0 °C to 85 °C (Commercial)
Configuration Method JTAG / serial configuration PROM —
Embedded Memory Dual-port RAM blocks (ESB) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Programming Toolchain Altera Quartus / MAX+PLUS II —
Series — APEX 20K
Family — APEX 20K (non-KE)
System Gates — 100,000
Logic Elements — 4,160
Maximum Logic Blocks — 26
Embedded Memory (RAM bits) — 53,248
User I/O Pins — 252
Total RAM bits — 53,248
Process Technology — 0.22 µm CMOS
Maximum Internal Frequency — 167 MHz
Propagation Delay — 1.6 ns
Speed Grade — -3 (slowest)
Package Body Size — 45 x 45 mm
Ball Pitch — 1.27 mm
Programming Interface — IEEE 1149.1 JTAG
Uri ng Pagpapasok — Surface Mount
Lead-Free — [DATA_NEEDED: lead-free status]

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