EP20K100FC324-2X vs EP20K100EFC324-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100FC324-2X sa pamamagitan ng Altera at EP20K100EFC324-2X sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K100FC324-2X - APEX 20K FPGA 100K Gates 324-BGA | Intel / Altera
EP20K100FC324-2X Obsolete
Pagsanggunian na paghahambing
| Parametro | EP20K100FC324-2X | EP20K100EFC324-2X |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX-20K | APEX 20KE |
| Logic Elements | 4,160 | — |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Maximum User I/O | 252 | — |
| Embedded RAM Bits | 53,248 | — |
| Operating Frequency (max) | 200 MHz | — |
| Propagation Delay | 1.6 ns | 1.6 ns |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS (all-layer copper metal) |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 3.3 V (5 V tolerant I/O) | — |
| Packhaging | 324-ball FineLine BGA (FBGA) | 324-ball FBGA (FineLine BGA), 19x19 mm, 1.27 mm pitch |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 °C to +85 °C (Commercial) | 0 °C to 85 °C (Commercial) |
| Configuration Interface | JTAG (IEEE 1149.1) / Serial / Parallel | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: confirm against lot-specific documentation] |
| Device Type | — | SPLD / FPGA (Field Programmable Gate Array) |
| System Gates | — | 100,000 gates |
| Logic Elements / Cells | — | 4,160 |
| Total RAM Bits | — | 53,248 bits |
| LABs / CLBs | — | 416 |
| Maximum User I/Os | — | 246 |
| Number of I/O Banks | — | 8 (per APEX 20KE family) |
| Internal Operating Frequency | — | Up to 250 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | — | -2X |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG, Altera configuration EPROM |