EP20K100QC240-1 vs EP20K100QC240-3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100QC240-1 sa pamamagitan ng Intel at EP20K100QC240-3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K100QC240-3N - 100K-Gate APEX-20K FPGA | Altera | Industrial
EP20K100QC240-3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP20K100QC240-1 | EP20K100QC240-3N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | APEX 20K | APEX-20K |
| Device Type | FPGA (Field-Programmable Gate Array) | FPGA |
| Logic Elements (LEs) | 4,160 | — |
| Typical Gates | 100,000 | — |
| Maximum User I/O | 189 | — |
| Embedded RAM Bits | 53,248 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | — |
| Maximum Internal Frequency | 250 MHz | — |
| Speed Grade | -1 | — |
| Packhaging | 240-pin PQFP (QFP-240) | 240-BFQFP |
| Package Code | S-PQFP-G240 | — |
| Terminal Form | Gull Wing | — |
| Propagation Delay | 1.6 ns (per datasheet, typical) | — |
| Temperature na Operasyon | 0 °C to +85 °C (Commercial) | 0 C to 85 C |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Programming | In-system (SRAM-based) via Quartus / MAX+PLUS II | — |
| Gate Count | — | 100000 gates |
| Logic Cells | — | 4160 cells |
| User I/O | — | 189 I/O |
| Distributed Memory | — | 53248 bits |
| Macrocells | — | 416 macrocells |
| Volte ng Pagbibigay | — | 2.375 V to 2.625 V |
| Nominal Supply | — | 2.5 V |
| Maximum Frequency | — | 167 MHz |
| Bilang ng Pin | — | 240 pins |
| Fabrication Process | — | 0.15 um all-layer copper-metal process |
| Package Pitch | — | 1.27 mm |
| Package Dimensions | — | 45 mm x 45 mm |
| Tindminan RoHS | — | unknown |
| AEC-Q100 | — | not_qualified |