EP20K100QC240-3 vs EP20K100QC240-3V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100QC240-3 sa pamamagitan ng Altera at EP20K100QC240-3V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K100QC240-3V - APEX 20KE FPGA 100K Gates 189 I/O 240-BFQFP | Intel
EP20K100QC240-3V ObsoletePagsanggunian na paghahambing
| Parametro | EP20K100QC240-3 | EP20K100QC240-3V |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Manufacturer | Altera | — |
| FPGA Family | APEX-20K | — |
| Number of Logic Elements | 4160 cells | — |
| Total RAM Bits | 53248 bits | 53,248 |
| Number of User I/O | 189 | 189 |
| Typical Gate Count | 263000 gates | — |
| Core Supply Voltage | 2.5 V | — |
| Maksimum na Taktiko ng Oras | 167 MHz (family rating) | — |
| Speed Grade | -3 | -3 (fastest APEX 20KE grade) |
| Technology Process | 0.22 um | — |
| Package Type | 240-BFQFP | — |
| Bilang ng Pins | 240 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Hanay ng Temperature na Operasyon | 0 °C to +85 °C (commercial) | — |
| Propagation Delay | [DATA_NEEDED: propagation delay timing table] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration / JTAG Interface | [DATA_NEEDED: configuration and JTAG interface details] | — |
| RoHS Compliance | [DATA_NEEDED: RoHS compliance for non-N version] | — |
| Series | — | APEX-20KE |
| Family | — | APEX-20K |
| Logic Logic Elements / Cells | — | 4,160 |
| Total System Gates | — | 100,000 |
| Number of Logic Blocks | — | 53248 (LABs) |
| Core Voltage | — | 2.375 V to 2.625 V |
| Temperature na Operasyon | — | 0C to +85C (Commercial) |
| Maximum Frequency | — | 167 MHz |
| Process Technology | — | 0.22 µm CMOS |
| Packhaging | — | 240-BFQFP (32 x 32 mm) |
| Lead-Free / RoHS | — | Yes (-3V suffix) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |