EP20K1500CF33C8ES vs EP20K1000CF672C8ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K1500CF33C8ES sa pamamagitan ng Intel at EP20K1000CF672C8ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K1000CF672C8ES - 1M-gate APEX20KE FPGA, 672-BGA | Intel
EP20K1000CF672C8ES ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K1500CF33C8ES | EP20K1000CF672C8ES |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Series | APEX 20K (APEX 20KE family) | — |
| Manufacturer | Intel (formerly Altera) | — |
| System Gates | 1,500,000 | — |
| Maximum Gates (Equivalent) | 2,392,000 | — |
| Logic Elements | 51,840 | 38,400 |
| Embedded System Block (ESB) Bits | 442,368 | — |
| CAM Bits | 216 Kbit | — |
| Number of PLLs | 4 | — |
| Number of Clocks | 8 clock pins | — |
| Maximum User I/O | 808 (1020-FBGA) | — |
| Packhaging | 1020-FBGA (FCBGA), 33x33 mm | 672-ball FineLine BGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Speed Grade | -1 (C8) | C8 |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | Commercial (0C to +85C) |
| Voltage - Supply (Core) | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) | — |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Programming Interface | ByteBlaster / MasterBlaster / Altera USB-Blaster | JTAG (IEEE 1149.1 / IEEE 1532) |
| Sample Tier | ES (engineering sample) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance for ES variant] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | APEX 20K (APEX20KE) |
| Typical Gates | — | 25,920 |
| Maximum System Gates | — | 1,000,000 |
| Embedded Memory (ESB) | — | 216 Kbits |
| User I/O Pins | — | 508 |
| Process Technology | — | 0.18 µm CMOS |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, LVDS, LVPECL, GTL, SSTL-2/3 |
| PLLs | — | 4 (ClockLock/ClockBoost) |
| Level ng MSL | — | 3 (168 hours) |