EP20K1500EBC652-1X vs EP20K1000EBC652-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K1500EBC652-1X sa pamamagitan ng Altera at EP20K1000EBC652-2X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K1500EBC652-1X - APEX 20KE 1.5M Gates FPGA | Altera | BGA-652
EP20K1500EBC652-1X ObsoleteAltera
EP20K1000EBC652-2X - 1M Gate APEX-20KE FPGA, 488 I/O, 652-BGA | Altera (Intel)
EP20K1000EBC652-2X NrndPagsanggunian na paghahambing
| Parametro | EP20K1500EBC652-1X | EP20K1000EBC652-2X |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX 20KE | APEX-20KE |
| Logic Elements / Cells | 51840 | — |
| System Gates | 1.5 M | — |
| Macros | 3456 | — |
| Total RAM Bits | 442368 | — |
| User I/O | 488 | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Propagation Delay | 1.84 ns | 1.6 ns |
| Internal Frequency | 160 MHz (per digchip) / 400 MHz (per fpgakey) | — |
| Core Voltage | 1.8 V | 1.8 V |
| Process Technology | 0.22 µm CMOS | 0.22 µm (some sources 0.15 µm) all-layer copper-metal CMOS |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Packhaging | 652-ball BGA (FCBGA / PBGA652) | 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Compliant |
| Configuration Method | JTAG / SRAM | — |
| Architecture | MultiCore (LUT + product-term) | — |
| Device Logic Elements | — | 38,400 |
| Typical Gates | — | 1,000,000 system gates |
| Embedded Memory Bits | — | 327,680 bits |
| User I/O Pins | — | 488 |
| Maximum User I/O | — | 488 |
| Internal Maximum Frequency | — | 350 MHz |
| Logic Blocks / Macros | — | 2,560 macros |
| PLLs | — | 4 |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Altera configuration |