EP20K160EQC240-1X vs EP20K160EQC240-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K160EQC240-1X sa pamamagitan ng Intel at EP20K160EQC240-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K160EQC240-1X | EP20K160EQC240-2 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | APEX 20KE | APEX 20KE |
| Logic Elements / Cells | 6,400 | — |
| System Gates | 160,000 | — |
| Embedded Memory (ESB) | [DATA_NEEDED: ESB RAM bits] | — |
| Maximum Internal Frequency | 373 MHz | — |
| Propagation Delay | 1.55 ns | 1.55 ns |
| User I/Os | 175 (some sources list 271 for BGA variant) | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.22 µm CMOS | 0.18-micron SRAM CMOS |
| Packhaging | 240-pin PQFP (FQFP) | PQFP-240 (QFP-240, FQFP) |
| Logic Family | CMOS | CMOS |
| Speed Grade | -1X (slowest commercial) | -2 |
| Temperature na Operasyon | 0 °C to +85 °C | 0 C to 85 C (Commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (Gull Wing) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (original Altera-era PQFP) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Typical Gates | — | 160,000 |
| Logic Elements (LEs) | — | 6,400 |
| Embedded System Blocks (ESBs) | — | 64 |
| Maximum Embedded Memory | — | 56 Kbits (approx. 7 Kbytes usable) |
| Maximum User I/O (this package) | — | 175 |
| Maximum User I/O (largest package) | — | 271 |
| PLLs | — | 4 |
| Internal Frequency (max) | — | 160 MHz |
| Bilang ng Pin | — | 240 |
| Supply Voltage (core) | — | [DATA_NEEDED: core VCC value] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, GTL+, LVDS |
| Configuration Modes | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| JTAG Support | — | IEEE Std. 1149.1 boundary-scan |
| MultiCore Architecture | — | Yes (Logic + ESB + I/O) |
| 5.0 V Tolerance | — | Achievable with external resistor |