EP20K200BC356-1 vs EP20K200EBC356-1N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200BC356-1 sa pamamagitan ng Altera at EP20K200EBC356-1N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200BC356-1 | EP20K200EBC356-1N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Product Function | APEX-20K Field Programmable Gate Array (FPGA) | — |
| Logic Family | CMOS | — |
| Equivalent System Gates | 200K gates | — |
| Logic Elements / Cells | 8320 | 8,320 |
| Total RAM Bits | 106496 bits | — |
| Maksimum na Taktiko ng Oras | 250 MHz | — |
| Core Supply Voltage | 2.5 V | — |
| User I/O Count | 277 | — |
| Bilang ng Pins | 356 | — |
| Packhaging / Kaso | 356-LBGA | — |
| Package Code | LBGA | — |
| Package Shape | Square | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.22 um | 0.22 um CMOS |
| Propagation Delay (tPD) | 2.5 ns (from -1N variant listing) | — |
| Hanay ng Temperature na Operasyon | 0 to 85 C (commercial, per -1N variant listing) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] | [DATA_NEEDED: RoHS status] |
| Lead-Free Finish | [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] | — |
| Family | — | APEX 20KE |
| Series | — | APEX-20KE |
| Typical Gates | — | 200,000 |
| Number of Macrocells | — | 832 |
| User I/Os | — | 271 |
| Propagation Delay | — | 2.5 ns |
| Internal Frequency (max) | — | 367 MHz |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V (nominal 1.8 V) |
| I/O Supply Voltage | — | MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| Packhaging | — | 356-BGA (LBGA, 35 x 35 mm) |
| Temperature na Operasyon | — | 0 C to +85 C (commercial) |
| Level ng MSL | — | 3 (168 hours) |
| Logic Family / Architecture | — | CMOS, MultiCore (LUT + embedded memory) |
| Configuration Method | — | SRAM-based, in-system programmable |