EP20K200BC484-1X vs EP20K200CF484C7ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200BC484-1X sa pamamagitan ng Altera at EP20K200CF484C7ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K200BC484-1X - APEX-20K 200K-Gate FPGA 382 I/O 484-BGA | Altera
EP20K200BC484-1X ObsoletePagsanggunian na paghahambing
| Parametro | EP20K200BC484-1X | EP20K200CF484C7ES |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Product Family | APEX-20K | — |
| Series | EP20K200 | APEX 20KC |
| Logic Elements / Cells | 8320 | 8,320 |
| Total RAM Bits | 106496 | 106,496 |
| Number of I/O | 382 | 377 (max) |
| Number of Logic Gates | 200000 | — |
| Package Type | 484-BBGA (Fine-pitch Ball Grid Array) | — |
| Package Suffix | BC484 | — |
| Speed Grade | -1 (slowest commercial grade) | C7 (7 ns) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (commercial, [DATA_NEEDED: full Tjj range]) | 0C to +85C (commercial) |
| Configuration Method | SRAM - external serial/parallel PROM | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| PLL | ClockLock / ClockBoost | — |
| Embedded Memory Blocks | Embedded System Blocks (ESBs) - RAM/ROM/CAM | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs_status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | APEX-20KC |
| Typical Gates | — | 200,000 |
| Number of LABs/CLBs | — | 376 |
| Voltage - Supply | — | 1.8 V core |
| Packhaging / Kaso | — | 484-BBGA (FineLine BGA) |
| Process Technology | — | 0.18 µm CMOS |
| Silicon Status | — | ES (Engineering Sample) |
| Maximum Internal Frequency | — | 375.94 MHz |
| Number of PLLs | — | [DATA_NEEDED: pll_count] |