EP20K200CB356C7N vs EP20K100CB356C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200CB356C7N sa pamamagitan ng Intel at EP20K100CB356C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K200CB356C7N - APEX 20KC FPGA 200K Gates 356-BGA | Intel / Altera
EP20K200CB356C7N ObsoleteIntel
EP20K100CB356C7 - APEX20K FPGA 100K Gates 252 I/O 356-BGA | Intel
EP20K100CB356C7 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K200CB356C7N | EP20K100CB356C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | APEX 20KC | — |
| Series | EP20K200 | APEX20K |
| System Gates | 200,000 | — |
| Logic Elements / Cells | 8,320 | — |
| Maximum Operating Frequency | 3571.6 MHz (internal equivalent) | — |
| Propagation Delay | 1.48 ns | — |
| User I/Os | 263 | — |
| Input Terminals | 267 | — |
| Supply Voltage (Nominal) | 1.8 V | — |
| Process Technology | 0.15 um CMOS | 0.18 μm CMOS |
| Temperature na Operasyon | 0C to +85C (Commercial) | Commercial grade |
| Packhaging | 356-ball PBGA (S-PBGA) | 356-LBGA |
| Uri ng Pagpapasok | Surface Mount | — |
| Embedded Memory | ESBs (dual-port RAM/ROM/FIFO) | — |
| Clock Management | PLL with up to 4 outputs | — |
| JTAG Support | Yes (IEEE 1149.1) | — |
| In-System Programmable | Yes | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Intel (formerly Altera) |
| Typical Gates | — | 100,000 |
| Maximum Logic Elements | — | 53,248 |
| User I/O Pins | — | 252 |
| Embedded Memory (Bits) | — | 53,248 |
| Number of PLLs | — | 4 |
| Core Voltage | — | 2.5 V |
| I/O Standards Supported | — | 1.8V, 2.5V, 3.3V, 5V (MultiVolt) |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Speed Grade | — | C7 |