EP20K200CF484C8ES vs EP20K200CF484C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200CF484C8ES sa pamamagitan ng Altera at EP20K200CF484C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200CF484C8ES | EP20K200CF484C8 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Series | APEX-20KC | — |
| Family | APEX 20K | APEX 20KC |
| Logic Elements | 8,320 | 8,320 |
| System Gates | 200,000 | 200,000 |
| Embedded Memory (RAM bits) | 106,496 | — |
| Number of Logic Array Blocks (LABs) | 104 | — |
| Number of Embedded System Blocks (ESBs) | 13 | — |
| User I/O Pins (max) | 376 | — |
| PLLs | 4 | — |
| Core Voltage | 1.8 V | 1.8 V |
| Speed Grade | C8 (-8 commercial) | — |
| Packhaging | 484-pin FBGA (FineLine BGA) | 484-FBGA (FineLine BGA, 23x23 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | 0C to +85C (commercial) | Commercial (0C to +85C) |
| Process Node | 0.18 micron CMOS | — |
| Configuration Interface | JTAG (IEEE 1149.1) / Altera serial | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL, SSTL, HSTL, AGP | — |
| Lead Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Embedded Memory Bits | — | 106,496 bits |
| Maximum User I/O | — | 376 |
| Process Technology | — | 0.15 µm CMOS |
| Maximum Frequency | — | 301.21 MHz (per FPGAkey listing) |
| Embedded Memory Type | — | ESB (Embedded System Block) — RAM/ROM/CAM/FIFO |
| Configuration Modes | — | Passive Serial, Passive Parallel Synchronous, Active Serial |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, GTL+ |
| Tindminan RoHS | — | Non-compliant (per alterachips.com listing) |