EP20K200CF484I9 vs EP20K200CF484I9N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200CF484I9 sa pamamagitan ng Altera at EP20K200CF484I9N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K200CF484I9 EP20K200CF484I9N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Series APEX 20KC —
Family APEX 20KC (APEX 20K with ESB/CAM) APEX 20KC
Process Technology 0.15 um CMOS 0.15 µm CMOS
Typical Gates 200,000 —
Logic Elements (Cells) 8,320 —
Maximum User I/O 376 —
Dedicated Inputs 4 —
Total Terminals 484 (balls) —
Packhaging 484-ball FineLine BGA (FBGA), 1.00 mm pitch 484-pin FBGA (PBGA484), 1.0 mm pitch
Core Supply Voltage (VCCINT) 1.8 V nominal (1.71 V to 1.89 V) —
Operating Temperature Grade Industrial (I) —
Junction Temperature Range -40 C to +100 C —
Speed Grade -9 (lowest speed in EP20K200 family) I9 (industrial, highest-performance bin)
Configuration Method SRAM, JTAG in-system programmable —
Tindminan RoHS unknown - confirm with supplier (legacy part) Compliant
Lifecycle Obsolete - EOL announced by Altera/Intel in 2008 —
Logic Elements / Cells — 8,320
Maximum Gates — 200,000
Maximum Internal Frequency — 250 MHz
Core Supply Voltage — 1.8 V nominal (1.71 V to 1.89 V)
User I/O Count — 376 (368 user I/O + 4 dedicated inputs)
Temperature na Operasyon — [DATA_NEEDED: industrial temperature range -40C to +85C assumed for I-grade]
Programmable I/O Standards — LVTTL, LVCMOS, PCI
Configuration Interface — JTAG IEEE 1149.1, ByteBlaster/BitBlaster serial
On-chip Memory — Embedded System Blocks (ESBs) for distributed RAM/ROM
Lead-Free (Pb-free) — Yes (N suffix)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita