EP20K200EBC652-2X vs EP20K1000EBC652-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200EBC652-2X sa pamamagitan ng Altera at EP20K1000EBC652-2X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K1000EBC652-2X - 1M Gate APEX-20KE FPGA, 488 I/O, 652-BGA | Altera (Intel)
EP20K1000EBC652-2X NrndPagsanggunian na paghahambing
| Parametro | EP20K200EBC652-2X | EP20K1000EBC652-2X |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Series | APEX-20KE® | — |
| Family | APEX-20KE | APEX-20KE |
| Device Logic Elements | 8,320 | 38,400 |
| Number of LABs/CLBs | 832 | — |
| Total RAM Bits | 106,496 | — |
| Number of I/O Pins | 376 | — |
| Number of Gates | 200,000 (typical) | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Operating Temperature (TJ) | 0C to +85C | — |
| Packhaging | 652-BGA | 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.18 um CMOS | 0.22 µm (some sources 0.15 µm) all-layer copper-metal CMOS |
| I/O Standard Support | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL | — |
| Configuration Method | Serial or Parallel PROM, JTAG (IEEE 1149.1) | — |
| Lead-Free / RoHS | Compliant (per DigiKey listing) | — |
| Typical Gates | — | 1,000,000 system gates |
| Embedded Memory Bits | — | 327,680 bits |
| User I/O Pins | — | 488 |
| Maximum User I/O | — | 488 |
| Propagation Delay | — | 1.6 ns |
| Internal Maximum Frequency | — | 350 MHz |
| Logic Blocks / Macros | — | 2,560 macros |
| PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| Temperature na Operasyon | — | 0 °C to +85 °C (commercial) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Altera configuration |
| Tindminan RoHS | — | Compliant |