EP20K200EBC652-2X vs EP20K200EBC652-3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200EBC652-2X sa pamamagitan ng Altera at EP20K200EBC652-3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200EBC652-2X | EP20K200EBC652-3N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Series | APEX-20KE® | APEX 20KE (APEX-20KE®) |
| Family | APEX-20KE | — |
| Device Logic Elements | 8,320 | — |
| Number of LABs/CLBs | 832 | — |
| Total RAM Bits | 106,496 | — |
| Number of I/O Pins | 376 | — |
| Number of Gates | 200,000 (typical) | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | 1.71 V to 1.89 V (nominal 1.8 V) |
| Operating Temperature (TJ) | 0C to +85C | 0 °C to 85 °C (commercial) |
| Packhaging | 652-BGA | 652-ball BGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.18 um CMOS | 0.22 µm CMOS |
| I/O Standard Support | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL | — |
| Configuration Method | Serial or Parallel PROM, JTAG (IEEE 1149.1) | — |
| Lead-Free / RoHS | Compliant (per DigiKey listing) | — |
| Device Family | — | EP20K200 |
| System Gates | — | 200,000 |
| Logic Elements / Cells | — | 8,320 |
| Logic Array Blocks (LABs) | — | 832 |
| Macrocells | — | 832 |
| Embedded RAM | — | 106,496 bits |
| User I/Os (DigiKey listing) | — | 376 |
| User I/Os (digchip listing) | — | 277 |
| Propagation Delay | — | 2.33 ns |
| Internal Frequency (max) | — | 189 MHz |
| I/O Supply (LVDS-capable) | — | LVDS, 2.5 V referenced (per source variant) |
| Speed Grade | — | -3 (slowest in APEX 20KE family) |
| Configuration | — | JTAG (IEEE 1149.1), Passive Serial |
| Tindminan RoHS | — | Compliant |