EP20K200EBC652-2X vs EP20K300EBC652-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200EBC652-2X sa pamamagitan ng Altera at EP20K300EBC652-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200EBC652-2X | EP20K300EBC652-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Unknown |
| Series | APEX-20KE® | — |
| Family | APEX-20KE | — |
| Device Logic Elements | 8,320 | — |
| Number of LABs/CLBs | 832 | — |
| Total RAM Bits | 106,496 | 147456 bits |
| Number of I/O Pins | 376 | — |
| Number of Gates | 200,000 (typical) | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Operating Temperature (TJ) | 0C to +85C | — |
| Packhaging | 652-BGA | 652-BGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.18 um CMOS | — |
| I/O Standard Support | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL | — |
| Configuration Method | Serial or Parallel PROM, JTAG (IEEE 1149.1) | — |
| Lead-Free / RoHS | Compliant (per DigiKey listing) | — |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Device Family | — | APEX-20KE |
| Logic Cells | — | 11520 |
| Macros | — | 1152 |
| I/O Count | — | 408 |
| Volte ng Pagbibigay | — | 1.71 V to 1.89 V |
| Package Dimensions | — | 45 mm x 45 mm |
| Technology | — | 0.22 um (reported for family variant) |
| Maksimum na Taktiko ng Oras | — | 350 MHz (reported for family variant) |
| Configuration Technology | — | SRAM-based programmable logic (family description) |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Tindminan RoHS | — | unknown |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |