EP20K200EBC652-2X vs EP20K300EBC652-2 比較
詳細並排比較 EP20K200EBC652-2X 由 Altera 與 EP20K300EBC652-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K200EBC652-2X | EP20K300EBC652-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Unknown |
| Series | APEX-20KE® | — |
| Family | APEX-20KE | — |
| Device Logic Elements | 8,320 | — |
| Number of LABs/CLBs | 832 | — |
| Total RAM Bits | 106,496 | 147456 bits |
| Number of I/O Pins | 376 | — |
| Number of Gates | 200,000 (typical) | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Operating Temperature (TJ) | 0C to +85C | — |
| 封裝 | 652-BGA | 652-BGA |
| 安裝類型 | Surface Mount | Surface Mount |
| Process Technology | 0.18 um CMOS | — |
| I/O Standard Support | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL | — |
| Configuration Method | Serial or Parallel PROM, JTAG (IEEE 1149.1) | — |
| Lead-Free / RoHS | Compliant (per DigiKey listing) | — |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Device Family | — | APEX-20KE |
| Logic Cells | — | 11520 |
| Macros | — | 1152 |
| I/O Count | — | 408 |
| 供應電壓 | — | 1.71 V to 1.89 V |
| Package Dimensions | — | 45 mm x 45 mm |
| Technology | — | 0.22 um (reported for family variant) |
| 最大時脈頻率 | — | 350 MHz (reported for family variant) |
| Configuration Technology | — | SRAM-based programmable logic (family description) |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |
| RoHS 狀態 | — | unknown |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |