EP20K200EFC484-1 vs EP20K200FC484-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200EFC484-1 sa pamamagitan ng Altera at EP20K200FC484-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera
EP20K200EFC484-1 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K200EFC484-1 | EP20K200FC484-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | APEX 20KE | APEX 20K |
| Logic Elements / Cells | 8320 | 8320 |
| System Gates | 200000 | 200 K |
| Embedded Memory (Bits) | 106496 | — |
| Maximum User I/O | 376 | — |
| Number of PLLs | 4 | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Packhaging | 484-BGA (FineLine BGA) | 484-ball FBGA (FineLine BGA) |
| Package Ball Count | 484 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40 °C to +85 °C (industrial, inferred from grade code) | 0 °C to 85 °C (Commercial) |
| I/O Standard Support | LVDS, PCI, LVTTL, LVCMOS, SSTL, HSTL | — |
| Programming Interface | IEEE 1149.1 JTAG, passive serial, passive parallel | IEEE 1149.1 JTAG |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Level ng MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Embedded Memory (RAM bits) | — | 106,496 bits |
| Number of I/Os | — | 382 |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Core Supply Voltage | — | 2.5 V |
| Maximum Operating Frequency | — | 250 MHz |
| Propagation Delay | — | 2.5 ns |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Speed Grade | — | -1 (fastest bin) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |