EP20K200RC208-1 vs EP20K200RC208-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200RC208-1 sa pamamagitan ng Intel at EP20K200RC208-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K200RC208-1 - APEX 20K 200K Gates FPGA, 208-Pin RQFP | Intel / Altera
EP20K200RC208-1 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP20K200RC208-1 | EP20K200RC208-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | APEX-20K | APEX-20K MultiCore FPGA |
| Series | APEX 20K (200K gates) | APEX-20K |
| System Gates | 200,000 | 200,000 (typical) |
| Logic Elements / Cells | 8,320 | — |
| Embedded Memory (bits) | 106,496 | 106,496 |
| Maximum User I/O | 144 | 144 |
| Number of PLLs | 4 | — |
| Process Technology | 0.22 µm CMOS | [DATA_NEEDED: process node] |
| Core Supply Voltage | 2.5 V | — |
| I/O Standard Support | LVTTL, LVCMOS, 2.5 V/3.3 V PCI, 1.8 V LVDS | — |
| Maximum Internal Frequency | 250 MHz | — |
| Packhaging | 208-BFQFP (RQFP) with Exposed Pad, 28×28 mm | 208-BQFP / 208-RQFP with Exposed Pad |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Interface | Passive Serial, Passive Parallel, JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) + Altera legacy scheme |
| Temperature na Operasyon | Industrial range | -40C to +85C (industrial) |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| Level ng MSL | [DATA_NEEDED: MSL Level] | [DATA_NEEDED: MSL rating] |
| Logic Elements (LEs) | — | 8320 |
| Bilang ng Pin | — | 208 |
| Speed Grade | — | -2 (mid-speed, industrial) |
| Supply Voltage (Core) | — | [DATA_NEEDED: core VCC] |
| Supply Voltage (I/O) | — | 3.3 V (multi-standard I/O) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |