EP20K30EFC324-1 vs EP20K30EFC324-1X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K30EFC324-1 sa pamamagitan ng Altera at EP20K30EFC324-1X sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K30EFC324-1X - APEX 20KE FPGA, 30K Gates, 324-BGA | Intel / Altera
EP20K30EFC324-1X ObsoletePagsanggunian na paghahambing
| Parametro | EP20K30EFC324-1 | EP20K30EFC324-1X |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel) | — |
| Series | APEX-20K | APEX 20KE |
| Family | APEX-20KE (1.8V, LVDS) | APEX-20K® (MultiCore™ architecture) |
| Logic Elements (typical) | 30,000 (30KLE) | — |
| Typical Gates | [DATA_NEEDED: typical gate count] | — |
| Total RAM Bits | 24576 | — |
| Maximum User I/O | 128 | 128 |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Supply Voltage | [DATA_NEEDED: VCCIO range] | — |
| Packhaging | 324-FBGA (FineLine BGA, 19x19 mm) | 324-ball FBGA (FineLine BGA), 19x19 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Bilang ng Pin | 324 | — |
| Temperature Grade | Commercial (per Altera family specification) | — |
| Temperature na Operasyon | 0C to +85C (commercial grade per Altera family spec) | — |
| Process Technology | SRAM-based, 0.18 um | 0.22 µm CMOS |
| Configuration | Passive serial / passive parallel / JTAG | — |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Speed Grade | -1 | — |
| Level ng MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| PLLs | Up to 4 (per APEX-20KE family) | 4 |
| Typical Gate Count | — | 30,000 gates |
| Logic Elements (LEs) | — | 1,200 |
| Embedded Memory (RAM bits) | — | 24,576 |
| Dedicated Inputs | — | 4 |
| Core Supply Voltage | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Standard Support | — | LVDS, LVTTL, LVCMOS, PCI, SSTL |
| Logic Delay (tPD) | — | 1.91 ns |
| Maksimum na Taktiko ng Oras | — | 909 MHz (internal), 160 MHz (I/O per partstack summary) |
| Configuration Method | — | Passive Serial, JTAG, Fast Passive Parallel |
| Tindminan RoHS | — | Compliant |
| Operating Temperature Grade | — | Commercial (0 °C to +85 °C) per package suffix interpretation; industrial on -1X grade [DATA_NEEDED: exact Tj range] |