EP20K400BC652-1V vs EP20K400BC652-1XVQ Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400BC652-1V sa pamamagitan ng Altera at EP20K400BC652-1XVQ sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400BC652-1V | EP20K400BC652-1XVQ |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KC | — |
| Family | APEX 20K | APEX 20K |
| Device Sub-Family | EP20K400 | — |
| System Gates | 1,052,000 | — |
| Maximum Logic Elements | 212,992 | — |
| Macrocells / LABs | 16640 | — |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 502 | — |
| Speed Grade | -1 | -1 (slowest) |
| Clock-to-Output (Tco) | 2.5 ns | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V | — |
| Packhaging | 652-BGA (FineLine, 45 x 45 mm) | 652-ball BGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (commercial) | -40C to +85C (industrial) |
| Configuration | SRAM-based, JTAG IEEE 1149.1 | — |
| Architecture | MultiCore (LUT + product-term + ESB) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Maximum System Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Logic Elements | — | 21,600 |
| Embedded Memory Bits | — | 212,992 |
| Maximum User I/O Pins | — | 488 |
| Supply Voltage Core | — | 1.8 V |
| I/O Standard Support | — | LVDS, LVTTL, LVCMOS, PCI, HSTL, SSTL |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |