EP20K400BC652-3V vs EP20K400BC652-1V Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400BC652-3V sa pamamagitan ng Altera at EP20K400BC652-1V sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400BC652-3V EP20K400BC652-1V
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20K APEX 20K
Series APEX-20K® APEX-20KC
Logic Cells / Elements 16,640 —
Gates 400,000 —
Total RAM Bits 212,992 —
User I/Os 502 —
Dedicated Inputs 4 —
Maximum Operating Frequency 167 MHz —
Propagation Delay 3.6 ns (per MicrochipUSA) —
Core Supply Voltage (VCCINT) 2.375 V to 2.625 V (nominal 2.5 V) —
I/O Supply Voltage (VCCIO) [DATA_NEEDED: banked VCCIO range] —
Process Technology 0.22 µm CMOS —
Temperature na Operasyon 0 °C to 85 °C (commercial) 0C to +85C (commercial)
Packhaging 652-ball BGA, 45 x 45 mm, 1.27 mm pitch 652-BGA (FineLine, 45 x 45 mm)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Speed Grade -3 (faster) -1
Tindminan RoHS [DATA_NEEDED: check distributor listing] [DATA_NEEDED: RoHS compliance]
Device Sub-Family — EP20K400
System Gates — 1,052,000
Maximum Logic Elements — 212,992
Macrocells / LABs — 16640
Embedded Memory (bits) — 212,992
Maximum User I/O — 502
Clock-to-Output (Tco) — 2.5 ns
Core Voltage (VCCINT) — 1.8 V
I/O Voltage (VCCIO) — 2.5 V
Configuration — SRAM-based, JTAG IEEE 1149.1
Architecture — MultiCore (LUT + product-term + ESB)

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