EP20K400CB652C9ES vs EP20K400BI652-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CB652C9ES sa pamamagitan ng Intel at EP20K400BI652-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CB652C9ES | EP20K400BI652-2 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Series | APEX 20KC | APEX-20KC |
| Family | APEX 20KC | APEX 20K |
| Logic Elements / Cells | 16640 | 16640 |
| Total System Gates | 400000 | — |
| Embedded Memory (Bits) | 212992 | — |
| Number of User I/O | 488 | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Number of Logic Array Blocks | 1040 | — |
| Maximum Operating Frequency | 250 MHz | — |
| Core Voltage | 1.8 V | 1.71 V to 1.89 V |
| Process Technology | 0.15 µm CMOS | 0.22 µm CMOS |
| Hanay ng Temperature na Operasyon | 0°C to +85°C (Commercial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Packhaging / Kaso | 652-BGA | — |
| Level ng MSL | 3 (168 Hours) | — |
| Packaging | Tray | — |
| Programmability Type | In-system programmable (SRAM-based) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL | — |
| JTAG (IEEE 1149.1) | Yes | — |
| PLL | Yes (4-phase) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| System Gates | — | 400000 |
| Total RAM Bits | — | 212992 |
| Number of Logic Array Blocks (LABs) | — | 502 |
| User I/O Count | — | 502 (max per family) |
| Number of I/O Banks | — | 8 |
| I/O Voltage Reference | — | 2.5 V (LVDS support) |
| Maximum Frequency | — | 200 MHz |
| Pin-to-Pin Delay (Tpd) | — | 3.1 ns |
| Packhaging | — | 652-BGA (45 x 45 mm) |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature grade] |