EP20K400CB652C9ES vs EP20K400BI652-2 比較
詳細並排比較 EP20K400CB652C9ES 由 Intel 與 EP20K400BI652-2 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400CB652C9ES | EP20K400BI652-2 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Series | APEX 20KC | APEX-20KC |
| Family | APEX 20KC | APEX 20K |
| Logic Elements / Cells | 16640 | 16640 |
| Total System Gates | 400000 | — |
| Embedded Memory (Bits) | 212992 | — |
| Number of User I/O | 488 | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Number of Logic Array Blocks | 1040 | — |
| Maximum Operating Frequency | 250 MHz | — |
| Core Voltage | 1.8 V | 1.71 V to 1.89 V |
| Process Technology | 0.15 µm CMOS | 0.22 µm CMOS |
| 工作溫度範圍 | 0°C to +85°C (Commercial) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 封裝 / 外殼 | 652-BGA | — |
| MSL 等級 | 3 (168 Hours) | — |
| Packaging | Tray | — |
| Programmability Type | In-system programmable (SRAM-based) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL | — |
| JTAG (IEEE 1149.1) | Yes | — |
| PLL | Yes (4-phase) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| System Gates | — | 400000 |
| Total RAM Bits | — | 212992 |
| Number of Logic Array Blocks (LABs) | — | 502 |
| User I/O Count | — | 502 (max per family) |
| Number of I/O Banks | — | 8 |
| I/O Voltage Reference | — | 2.5 V (LVDS support) |
| Maximum Frequency | — | 200 MHz |
| Pin-to-Pin Delay (Tpd) | — | 3.1 ns |
| 封裝 | — | 652-BGA (45 x 45 mm) |
| 工作溫度 | — | [DATA_NEEDED: operating temperature grade] |