EP20K400CF672C-8 vs EP20K400CF672C7ES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CF672C-8 sa pamamagitan ng Altera at EP20K400CF672C7ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400CF672C-8 EP20K400CF672C7ES
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20K APEX 20KC
Logic Elements 16,640 —
Typical Gates 400,000 —
Macros 1,664 —
Maximum User I/O 488 488
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Package Type PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) 672-ball FineLine BGA
Core Voltage (VCCINT) 1.8 V nominal (1.71 V to 1.89 V) —
I/O Voltage (VCCIO) [DATA_NEEDED: VCCIO options] —
Pin-to-Pin Delay (tPD) 1.78 ns (speed grade -8) —
Speed Grade -8 C7 (commercial, -7)
Temperature Grade (C) Commercial, 0 °C to 85 °C —
Process Technology 0.15 µm all-layer copper CMOS 0.18 um CMOS
Embedded Memory Type ESB (RAM / ROM / CAM) —
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Passive Parallel —
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Level ng MSL [DATA_NEEDED: MSL level] —
Series — EP20K400
Device Type — Loadable PLD / FPGA
Logic Elements (Cells) — 16,640
System Gates — 400,000
Embedded Memory (Bits) — 212,992
Total RAM Bits — 212,992
I/O Lines — 484
Input Lines — 488
Number of PLLs — 4
Maximum Internal Clock Frequency — 375.94 MHz
Propagation Delay — 1.4 ns
Core Voltage — 1.8 V
MultiVolt I/O — 1.5 V / 1.8 V / 2.5 V / 3.3 V
Temperature na Operasyon — 0C to +85C (commercial)
Package Code — FC-FBGA-B672
Ball Pitch — 1.000 mm

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