EP20K400CF672C-8 vs EP20K400CF672C7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CF672C-8 sa pamamagitan ng Altera at EP20K400CF672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400CF672C-8 EP20K400CF672C7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20K APEX 20KC
Logic Elements 16,640 —
Typical Gates 400,000 400,000
Macros 1,664 —
Maximum User I/O 488 488
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Package Type PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) —
Core Voltage (VCCINT) 1.8 V nominal (1.71 V to 1.89 V) 1.8 V
I/O Voltage (VCCIO) [DATA_NEEDED: VCCIO options] 3.3 V / 2.5 V banked
Pin-to-Pin Delay (tPD) 1.78 ns (speed grade -8) —
Speed Grade -8 —
Temperature Grade (C) Commercial, 0 °C to 85 °C —
Process Technology 0.15 µm all-layer copper CMOS 0.18-micron CMOS, all-layer copper interconnect
Embedded Memory Type ESB (RAM / ROM / CAM) —
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Passive Parallel —
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount (BGA)
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status not in provided data]
Level ng MSL [DATA_NEEDED: MSL level] 3 (per JEDEC J-STD-020)
Maximum System Gates — 1,052,000
Logic Elements (LEs) — 16,640
Embedded Memory — 488 Kbits
User I/O (per catalog) — 480 / 502 (per source)
Packhaging — 672-ball FineLine BGA (FC-FBGA / BBGA)
Propagation Delay — 2.5 ns (catalog) / 1.48 ns (some catalog)
Maximum Frequency — 375.94 MHz (internal)
Temperature na Operasyon — 0 C to 85 C (Commercial)
Configuration Modes — PS, PPS, JTAG

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