EP20K400CF672C-8 vs EP20K400CF672C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CF672C-8 sa pamamagitan ng Altera at EP20K400CF672C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CF672C-8 | EP20K400CF672C8 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KC |
| Logic Elements | 16,640 | 16,640 |
| Typical Gates | 400,000 | — |
| Macros | 1,664 | 1,664 |
| Maximum User I/O | 488 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Package Type | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) | — |
| Core Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO options] | — |
| Pin-to-Pin Delay (tPD) | 1.78 ns (speed grade -8) | — |
| Speed Grade | -8 | C8 |
| Temperature Grade (C) | Commercial, 0 °C to 85 °C | — |
| Process Technology | 0.15 µm all-layer copper CMOS | — |
| Embedded Memory Type | ESB (RAM / ROM / CAM) | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Series | — | APEX 20K |
| System Gates | — | 400,000 |
| Max User I/Os | — | 488 |
| Embedded RAM Bits | — | 212,992 |
| Core Voltage | — | 2.5 V |
| Logic Family | — | CMOS |
| Propagation Delay | — | 2.5 ns |
| Packhaging | — | 672-ball FineLine BGA (FC-FBGA) |
| Package Type Code | — | BGA-652 |
| Temperature na Operasyon | — | 0C to 85C |