EP20K400CF672I7 vs EP20K400CF672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CF672I7 sa pamamagitan ng Intel at EP20K400CF672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CF672I7 | EP20K400CF672C7N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 16,640 | — |
| Maximum System Gates | 400,000 | 1,052,000 |
| Embedded Memory (ESB) | 212,992 bits | — |
| Maximum User I/O Pins | [DATA_NEEDED: pin count for CF672 package] | — |
| Process Technology | 0.15 um CMOS | 0.18-micron CMOS, all-layer copper interconnect |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltage | 1.8 V / 3.3 V | — |
| PLL Count | 4 | — |
| Temperature na Operasyon | -40 C to +85 C (industrial) | 0 C to 85 C (Commercial) |
| Speed Grade | I7 | — |
| Packhaging | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) | 672-ball FineLine BGA (FC-FBGA / BBGA) |
| Terminal Finish | Tin/Lead (Sn/Pb) | — |
| JESD-609 Code | e0 | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 | — |
| Configuration Mode | PS / AS / JTAG (IEEE 1149.1) | — |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Embedded Memory | — | 488 Kbits |
| Maximum User I/O | — | 488 |
| User I/O (per catalog) | — | 480 / 502 (per source) |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 3.3 V / 2.5 V banked |
| Propagation Delay | — | 2.5 ns (catalog) / 1.48 ns (some catalog) |
| Maximum Frequency | — | 375.94 MHz (internal) |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status not in provided data] |
| Configuration Modes | — | PS, PPS, JTAG |