EP20K400CFC672-9 vs EP20K400FC672-1XGZ Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CFC672-9 sa pamamagitan ng Altera at EP20K400FC672-1XGZ sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400CFC672-9 EP20K400FC672-1XGZ
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family APEX-20KC APEX-20KE
Logic Elements / Macrocells 1664 —
Typical Gate Count 400,000 gates —
Embedded Memory (ESB) 212,992 bits —
User I/O Count 488 —
PLLs 4 —
Core Supply Voltage 1.71 V to 1.89 V 2.5 V
I/O Supply Voltage 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Operating Temperature (TJ) 0 °C to 85 °C —
Speed Grade -9 (commercial, slowest bin) -1 (slowest commercial bin)
Packhaging 672-ball FineLine BGA (FCBGA) 672-pin FBGA (Fine-pitch BGA)
Package Body Size 27 mm × 27 mm —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Configuration Method EPC serial device or JTAG JTAG / passive serial / passive parallel (per APEX-20KE handbook)
Process Node [DATA_NEEDED: process node] —
Tindminan RoHS [DATA_NEEDED: RoHS status] Unknown (legacy part, pre-dates widespread RoHS conversion)
Logic Elements / Cells — 16,640
System Gates — 400,000 (typical)
Embedded Memory Bits — 212,992
Maximum User I/O — 502
Temperature na Operasyon — 0C to +85C (commercial)
Propagation Delay — 2.5 ns (per DigiChip listing)
Logic Family / Process — CMOS
Level ng MSL — [DATA_NEEDED: MSL level per JEDEC J-STD-020]
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+ (per APEX-20KE family datasheet)

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