EP20K400FC672-1XGZ vs EP20K400FI672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FC672-1XGZ sa pamamagitan ng Intel at EP20K400FI672-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K400FC672-1XGZ - 400K Gate APEX-20KE FPGA, 502 I/O, 672-FBGA | Intel
EP20K400FC672-1XGZ ObsoleteAltera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400FC672-1XGZ | EP20K400FI672-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX-20KE | APEX-20K |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (typical) | — |
| Embedded Memory Bits | 212,992 | 212992 |
| Maximum User I/O | 502 | — |
| Packhaging | 672-pin FBGA (Fine-pitch BGA) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | 0 °C to +85 °C (Commercial) |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Propagation Delay | 2.5 ns (per DigiChip listing) | 2.5 ns |
| Logic Family / Process | CMOS | — |
| Speed Grade | -1 (slowest commercial bin) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Level ng MSL | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | — |
| Tindminan RoHS | Unknown (legacy part, pre-dates widespread RoHS conversion) | Lead-free / RoHS Compliant |
| Configuration Method | JTAG / passive serial / passive parallel (per APEX-20KE handbook) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ (per APEX-20KE family datasheet) | — |
| Logic Elements | — | 16640 |
| Maximum Gates | — | 400,000 gates |
| User I/Os | — | 502 |
| Number of Macros | — | 1664 |
| Process Technology | — | 0.22 µm CMOS |
| Maximum Internal Frequency | — | 200 MHz |
| Package Type | — | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) |
| PLLs (Phase-Locked Loops) | — | 4 |
| Configuration Modes | — | JTAG, Passive Serial, Passive Parallel |