EP20K400FC672-3X vs EP20K400FC672-3V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FC672-3X sa pamamagitan ng Altera at EP20K400FC672-3V sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera
EP20K400FC672-3X ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP20K400FC672-3X | EP20K400FC672-3V |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Logic Family | APEX 20K | — |
| Device Sub-family | EP20K400 | — |
| Technology | CMOS 0.22 µm | — |
| Number of Gates | 400,000 (typical) | — |
| Logic Cells | 16,640 | — |
| Macros / Macrocells | 1664 | — |
| User I/Os | 502 | — |
| Dedicated I/O Lines | 496 | — |
| Core Supply Voltage | 2.5 V | — |
| Maksimum na Taktiko ng Oras | 181.82 MHz | — |
| Typical Propagation Delay | 2.07 ns | — |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| Speed Grade | -3X | -3 |
| Packhaging | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) | — |
| Architecture | MultiCore (LUT + embedded CAM/RAM) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Family | — | APEX 20KC |
| Series | — | APEX-20KC |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements / Cells | — | 16640 |
| System Gates | — | 400000 |
| Total RAM Bits | — | 212992 |
| Number of I/O | — | 502 |
| Number of LABs/CLBs | — | 1664 |
| Number of Logic Elements | — | 16640 |
| Supply Voltage (Core) | — | 1.71 V to 1.89 V |
| Packhaging / Kaso | — | 672-BBGA, FCBGA |
| Supplier Device Package | — | 672-FBGA (27x27) |
| Process Technology | — | 0.22 µm |
| Maximum Internal Frequency | — | 167 MHz (typical) |
| Pin-to-Pin Delay | — | 3.6 ns |
| Programmability Type | — | In-system (JTAG IEEE 1149.1) |