EP20K400FI672-2V vs EP20K400FI672-2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-2V sa pamamagitan ng Intel at EP20K400FI672-2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400FI672-2V | EP20K400FI672-2N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | APEX 20K | APEX 20K |
| Device | EP20K400 | — |
| Logic Elements / Cells | 16640 | 16,640 |
| Total System Gates | 400000 | — |
| Embedded Memory Bits | 212992 | 212,992 bits |
| Number of I/O | 502 | — |
| Packhaging | 672-BBGA, FCBGA | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Pin / Ball Count | 672 | — |
| Volte ng Pagbibigay | 2.5 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Propagation Delay | 2.5 ns | 3.1 ns |
| Internal Operating Frequency | 200 MHz | — |
| Temperature na Operasyon | 0 °C to +85 °C | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] |
| Logic Family | CMOS | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Configuration Mode | Serial / Parallel / JTAG | — |
| Tindminan RoHS | [DATA_NEEDED: rohs] | Compliant (lead-free) |
| Level ng MSL | [DATA_NEEDED: msl] | — |
| Typical Gates | — | 400,000 |
| Maximum User I/O | — | 488 |
| Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count per family datasheet] |
| Core Voltage | — | 2.5 V |
| Maximum Frequency | — | 200 MHz |
| Package Body Size | — | 27 x 27 mm |
| Terminal Pitch | — | 1.0 mm |
| Speed Grade | — | -2 |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 °C |
| Configuration Modes | — | PS, PPS, PPA, JTAG |
| Supported I/O Standards | — | LVTTL, LVCMOS, SSTL, HSTL |