EP20K400FI672-2X vs EP20K400PI655-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-2X sa pamamagitan ng Intel at EP20K400PI655-2X sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K400PI655-2X - APEX 20K 400K Gates FPGA, 655-Pin PQFP | Intel / Altera
EP20K400PI655-2X ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400FI672-2X | EP20K400PI655-2X |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | APEX 20K | APEX 20K |
| Logic Elements | 16,640 | — |
| Typical Gates | 400,000 system gates | — |
| Embedded Memory | 212,992 bits | — |
| User I/O Pins | 496 | — |
| Packhaging | 672-ball BGA (FI672) | PQFP-655 (Power Quad Flat Pack) |
| Package Code | BGA | — |
| Terminal Form | Ball | — |
| No. of Terminals | 672 | — |
| Package Shape | Square | — |
| Speed Grade | -2X | -2X |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Core Voltage | 1.8 V | 3.3 V |
| I/O Voltage Support | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) | — |
| Configuration Method | SRAM (serial EPROM or JTAG) | Serial / Parallel / JTAG |
| JTAG Support | Yes (IEEE 1149.1) | — |
| Process Technology | 0.18 um CMOS, 6-metal | 0.18 um CMOS |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Device Series | — | EP20K400 |
| Maximum Logic Elements | — | 16,640 |
| Maximum System Gates | — | 400,000 |
| Maximum RAM Bits | — | 166,400 |
| Embedded System Blocks (ESBs) | — | 104 |
| Maximum User I/O Pins | — | 488 |
| Maximum PLLs | — | 4 |
| I/O Standards | — | LVTTL, LVCMOS, PCI, GTL+ |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera APEX 20K family) |