EP20K400FI672-3 vs EP20K400FI672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-3 sa pamamagitan ng Altera at EP20K400FI672-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400FI672-3 | EP20K400FI672-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | APEX-20K |
| Series | EP20K400 | — |
| Logic Elements | 16640 | 16640 |
| Total Gates | up to 400000 | — |
| Embedded RAM | 212992 bits | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | — |
| Propagation Delay | 3.6 ns | 2.5 ns |
| Maksimum na Taktiko ng Oras | 833 MHz | — |
| Supply Voltage (Nominal) | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | 0.22 µm CMOS |
| Package Type | PBGA (Plastic BGA) | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) |
| Package Code | S-PBGA-B672 | — |
| Terminal Count | 672 | — |
| Terminal Pitch | 1.000 mm | — |
| Package Shape | Square BGA | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Configuration Interface | JTAG (IEEE 1149.1) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (Commercial) |
| Level ng MSL | 3 | — |
| Peak Reflow Temperature | 220 C | — |
| Maximum Gates | — | 400,000 gates |
| User I/Os | — | 502 |
| Embedded Memory Bits | — | 212992 |
| Number of Macros | — | 1664 |
| Core Supply Voltage | — | 2.5 V |
| Maximum Internal Frequency | — | 200 MHz |
| PLLs (Phase-Locked Loops) | — | 4 |
| Configuration Modes | — | JTAG, Passive Serial, Passive Parallel |
| Tindminan RoHS | — | Lead-free / RoHS Compliant |