EP20K400FI672-3V vs EP20K400FC672-3V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-3V sa pamamagitan ng Intel at EP20K400FC672-3V sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400FI672-3V | EP20K400FC672-3V |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K (EP20K400) | APEX 20KC |
| Logic Elements | 16,640 | — |
| Maximum Gates | 400,000 | — |
| Typical Gates | [DATA_NEEDED: typical gates value] | — |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | — |
| Total User I/O + Dedicated Inputs | 496 + 6 (variant dependent) | — |
| Maksimum na Taktiko ng Oras | 714.2 MHz | — |
| Speed Grade | -3 (faster) | -3 |
| Core Voltage (VCCINT) | 2.5 V nominal (2.375 V to 2.625 V) | — |
| Process Technology | 0.18 µm CMOS, 4 metal layers | 0.22 µm |
| Packhaging | 672-ball FineLine BGA (BBGA), 1.0 mm pitch | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable via JTAG | Yes (IEEE 1149.1) | — |
| Supported I/O Standards | LVCMOS, LVTTL, SSTL, GTL+, HSTL | — |
| Configuration Modes | JTAG, passive serial, passive parallel | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | [DATA_NEEDED: operating temperature range] |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Series | — | APEX-20KC |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements / Cells | — | 16640 |
| System Gates | — | 400000 |
| Total RAM Bits | — | 212992 |
| Number of I/O | — | 502 |
| Number of LABs/CLBs | — | 1664 |
| Number of Logic Elements | — | 16640 |
| Supply Voltage (Core) | — | 1.71 V to 1.89 V |
| Packhaging / Kaso | — | 672-BBGA, FCBGA |
| Supplier Device Package | — | 672-FBGA (27x27) |
| Maximum Internal Frequency | — | 167 MHz (typical) |
| Pin-to-Pin Delay | — | 3.6 ns |
| Programmability Type | — | In-system (JTAG IEEE 1149.1) |